1. Field of the Invention
The present invention relates to a re-configurable Viterbi decoder. By re-setting the values of some registers, the inside control path and data path of the Viterbi decoder can be appropriately changed so as to meet the requirements of different communication systems.
2. Description of the Prior Art
In the wireless communication system, the data has to be transmitted through the air by modulating the information signal on the radio-frequency electromagnetic wave. In the receiver, the information signal is recovered from the received electromagnetic wave. However, in the transmission process, the interference inevitably happens and is partially caused by the thermal noise in the natural. Furthermore, most part of the interference is generated from the natural phenomenon of the electromagnetic wave transmission such as reflection or diffraction in the space. This causes the performance degradation in the receiver. In order to overcome this phenomenon, many communication theories and methods are proposed and discussed in the past decades. The important one is the forward error correction (FEC) technique, which is one kind of error control code commonly used in the digital communication. When FEC is used in the process of transmission, the transmitter sends not only the information data but some redundant digits generated from the information data in a specific way. If any error occurs in the process of transmission, the error will be automatically corrected through the mechanism of FEC with the assist of the redundant digits in the receiver. In the known methods of the forward error correction, the convolutional code is a very critical one and widely used in modern communication systems. So far the most common method used for the decoding of convolutional code is the Viterbi algorithm. The Viterbi algorithm is a well-established technique for channel and source coding in high performance digital communication systems. When used for decoding of convolutional codes, the Viterbi algorithm is to perform a maximum-likelihood sequence detection on data that has been convolutionally encoded.
It is an inevitable trend in the future development of the telecommunication technology to combine the wireless communication and the broad band internet. However, for different communication system specifications, such as the wireless broad band local area network (WLAN) or the third generation of mobile communication system (3G), the required convolutional code specifications are also different. To develop a design which affords to offer multi-standard function, re-configurability at run time has to be considered. The prior art Viterbi decoder is designed for a specific convolutional code, and therefore, before designing, the characteristic of the specific convolutional code has to be known and fixed, including the constraint length, and the generator polynomial. According to these known parameters, the designer can manage the add-compare-select (ACS) mechanism, the branch metric calculator (BMC), the path metric storage unit (PMS unit), the path memory and the path tracing logic unit in the Viterbi decoder to meet different system requirement. For example, if the decoding speed is the main concern in the system, then the designer can use add-compare-select (ACS) units as many as possible. The trade off is the cost increase due to the large hardware area. On the other hand, if the hardware area is the main issue that the designer has to concern first, then the number of the add-compare-select (ACS) units will be reduced in some way.
Please refer to FIG. 1. FIG. 1 is a perspective diagram of a prior art non in-place decoder with four add-compare-select units. There are two banks of memory for the storage of path metrics. The data items to be decoded are inputted into the prior art decoder, and passed through a branch metric calculator 15 so as to calculate branch metrics and then separately send the calculated results to the first add-compare-select device 11, the second add-compare-select device 12, the third add-compare-select device 13 and the forth add-compare-select device 14. At the same time, the old path metrics are read out from the path metric storage unit and also sent to the add-compare-select (ACS) devices. The circuit inside the add-compare-select devices are described as FIG. 1B. Each add-compare-select device receives the branch metrics provided from the branch metric calculator 15 and old path metrics stored in the path metric storage unit 101 or 102 as inputs, and performs the add-compare-select (ACS) operation. The selected new path metrics are stored back to another path metric storage unit, and at the same time, the selection bit is stored in the path memory. The memory address is assigned by an address generator 19, and each of the path metrics is separately distributed to the add-compare-select devices (11,12,13,14) by the multiplexer 18. The generated selection bit is stored in the path memory 16, and a path tracing logic unit 17 will read out the selection bits so as to finish the decoding. This prior art technology can achieve the object of quick decoding, but it requires a greater memory size for storage of path metrics and a higher cost because of the usage of the non in-place method.
In the prior art, it is known to use the pipeline structure for decoding. Although this prior applies the in-place operation so as to reduce the memory space, however, it is hard for re-configurability. That is, it needs more design effort to decode different convolution code specified in different system with the pipeline structure for the Viterbi decoder by applying only one set of hardware.
In order to improve the drawbacks of the prior art, the present invention provides a re-configurable Viterbi decoder. By re-setting the values of some registers, the inside control path and data path of the Viterbi decoder can be appropriately changed so as to meet the requirements of different communication systems.